The present invention relates to an intelligent power switch and a switching apparatus, and more particularly to an intelligent power switch and a switching apparatus for use in an automobile and arranged to selectively supply electric power from a battery to each load.
Hitherto, a multiplicity of switching circuits have been mounted on a vehicle to selectively supply electric power from a battery to each electric units (hereinafter called as "loads") in response to operation of operation switches, such as an ignition key, a light switch, an audio switch and so forth.
FIG. 8 schematically shows the foregoing structure in which a battery 1 is connected to a junction block (J/B) 2. Operation switches SW1, SW2, . . . , disposed on an operation panel 3 are connected to the junction block 2. The junction block 2 has switching circuits corresponding to the number of the operation switches SW1, SW2, . . . . Each switching circuit switches on/off the connection between a power supply line from the battery 1 and each electric wire connected to each load in response to the operation of the operation switches SW1, SW2, . . . .
As a result, the battery power is, through the junction block 2, selectively supplied to each load in response to the operation of the operation switches SW1, SW2, . . . . When, for example, a head light switch is switched on, the junction block 2 turns on a power supply line from the battery 1 and electric wires connected to the head lights 4A and 4B. Thus, electric power is supplied to the head lights 4A and 4B so that the head lights 4A and 4B are turned on.
In addition to the head lights 4A and 4B which are loads to which electric power is directly supplied through the junction block 2, loads, such as motors 5A and 5B for operating the power windows, are supplied with electric power output from the junction block 2 through switching circuits 6A and 6B. The switching operations of the motors 5A and 5B are controlled by operation switches 7A and 7B.
In actuality, the junction block 2 is structured as shown in FIG. 9. The junction block 2 is provided with a plurality of relays L1, L2, L3, . . . . The foregoing relays L1, L2, L3, . . . , are classified into relays, such as the relays L1 and L2, to which the head lights 4A and 4B correspond and the switching operations of which are directly controlled by the operation switches SW1 and SW2 so as to directly supply electric currents to the loads; and the relay L3, the switching operation of which is controlled in accordance with the state of the ignition switch 8.
Among the above-mentioned relays, the relays L1 and L2 are supplied with electric power from the battery through a fusible link (FL) 9 and fuses F1 and F2. As a result, if a high electric current higher than an allowable level flows through a power supply line for establishing the connection between the battery 1 and the junction block 2, the fusible link 9 is fused. If an excess current higher than an allowable level flows in an electric wire (a harness) for establishing the junction block 2 and each load, the fuses F1 and F2 are fused. Thus, the overall body of the power supply line can be protected from smoking or firing, and flow of an excess current to a load can be prevented. Similarly, the relay L3 is supplied with battery power from the battery 1 through the fusible link FL9. Moreover, an output terminal of the relay L3 is connected to each of the loads 5A and 5B through the fuses F3 and F4 and the relays L4 and L5.
Since semiconductor switches having improved performance and low cost can easily be obtained because the technology for manufacturing semiconductors has been developed in recent years, a switching circuit using a semiconductor switch has been suggested to be employed in place of the relays L1, L2, L3, . . . , arranged to be operated by the mechanical contacts.
A switching circuit of the foregoing type is generally provided with a protective function for protecting the semiconductor switch from an excess current and overheat. In a case where an electric current higher than a predetermined level flows in the semiconductor switch or in a case where the semiconductor switch has been heated to a level higher than a predetermined temperature, the semiconductor switch is forcibly switched off so that the semiconductor switch is protected.
FIG. 10 shows an example of a switching circuit using the semiconductor switch of the foregoing type. A switching circuit 11 is connected to the positions of each of the relays L1, L2, . . . , in place of each of the relays L1, L2, . . . . In an example case where the switching circuit 11 is connected in place of the relay L1, a fuse F1 (see FIG. 9) is connected to a power supply terminal 12. A load 4A is connected to an output terminal 13. Moreover, an operation switch SW1 is connected to a control signal input terminal 14. In the case of the switching circuit 11, a control voltage generating portion (not shown) arranged to supply control voltage of, for example 5 V!, supplied from the operation switch SW1 to the control signal input terminal 14 as a switch-on control signal when the operation switch SW1 is switched on and to inhibit supply of the control voltage when the operation switch SW1 is switched off, is actually disposed between the operation switch SW1 and the control signal input terminal 14.
The switching circuit 11 is composed of an n-channel power MOS-FET 15 (hereinafter simply called as a "MOS-FET 15") serving as a main semiconductor switch and a protective circuit 16 for protecting the MOS-FET 15 from an excess current and overheat. The protective circuit 6 forcibly turns the MOS-FET 15 off when the level of the electric current which flows in the MOS-FET 15 or heat generated from the MOS-FET 15 exceeds a predetermined value so as to protect the MOS-FET 15. Note that the switching circuit 11 is structured by one chip.
When a control signal for instructing to switch the switching circuit 11 on is actually supplied from the control signal input terminal 14 (that is, when, for example, voltage of 5 V! is applied to the control signal input terminal 14 as control voltage V.sub.IN), input S of the RS flip-flop 17 is made to be "High" and output Q is made to be "High". Thus, the FET 18 is turned on. As a result, voltage sufficiently high to turn on the MOS-FET 15 is applied to the gate of the MOS-FET 15 so that the MOS-FET 15 is turned on.
Since an excess current flows in the MOS-FET 15 in a case where a load (not shown) connected to the output terminal 13 through an electric wire is short-circuited due to a failure or the like in the above-mentioned on-condition, or in a case where the power supply voltage VB is raised to an excess level, there arises a risk that the MOS-FET 15 may be damaged. Also in a case where the MOS-FET 15 is heated excessively, there arises a risk that the MOS-FET 15 may be broken owning to heat.
Therefore, the switching circuit 11 is structured such that comparators 20 and 21 monitor whether or not the level of the electric current which flows in the MOS-FET 15 and the temperature of the MOS-FET 15 are higher than predetermined levels to forcibly turn the MOS-FET 15 off if the levels are higher than the predetermined levels so as to prevent damage of the MOS-FET 15.
Specifically, source voltage (a voltage level converted by resistor R1 to be in proportion to a source electric current) of the MOS-FET 15 is supplied to a non-inverted input terminal of the comparator 20, while reference voltage Vref generated by a bias generating circuit 22 is supplied to an inversion input terminal. If the source voltage is higher than the reference voltage Vref, positive logic is output.
Voltage level V.sub.T in proportion to the temperature is supplied from a temperature sensor (not shown), disposed adjacent to the MOS-FET 15, to a non-inverted input terminal of the comparator 21, while the reference voltage Vref is supplied to the inverted input terminal of the same. If the temperature voltage V.sub.T is higher than the reference voltage Vref, positive logic is output. Thus, if an excess current flows in the MOS-FET 15 or if the MOS-FET 15 is overheated, a logical summation circuit 23 outputs a logical value of positive logic.
At this time, since the flip-flop 17 is supplied with the positive logic signal from the logical summation circuit 23 to the input R thereof, it outputs negative logic as output Q and positive logic as inverted output Q. As a result, the FET 18 is turned off and the FET 19 is turned on so that the gate of the MOS-FET 15 is not supplied with the control voltage V.sub.IN. Thus, the MOS-FET 15 is turned off. If excess voltage is supplied, the level of power supply voltage V.sub.B is lowered through a zener diode 24A and a diode 24B, and then the power supply voltage V.sub.B is applied to the gate of the MOS-FET 15. Thus, the electric current is allowed to pass through the gate of the MOS-FET 15, and then allowed to flow into the source.
A zener diode 15A provided for the MOS-FET 15 is a parasitic diode of the MOS-FET 15, and a zener diode 25 disposed between the control signal input terminal 14 and the output terminal 13 is arranged to bypass the control signal voltage V.sub.IN if it has been raised to a level higher than a predetermined level.
As a switching circuit using a semiconductor switch, a switching circuit called as "IPS (Intelligent Power Switch)" formed as shown in FIG. 11 has been suggested. The switching circuit 30 has an abnormal-signal output portion 41 for indicating abnormality of the switching circuit 30 in accordance with the output voltage level VOUT from the semiconductor switch.
The abnormal-signal output portion 41 is, as shown in FIG. 8, connected to the abnormal display portion 43 through a CPU (Central Processing Unit) 42 so as to detect forcible switching off of the semiconductor switch 32 because of the protective function of the switching circuit 30, which is operated if excessively high voltage is applied to the semiconductor switch 32 of the switching circuit 30, an excess current flows through the same or the same is overheated, so as to transmit an abnormal signal to the CPU 42. In accordance with the abnormal signal, the CPU 42 detects the switching circuit 30 which has encountered the abnormality, and then causes an abnormal display portion 43 to display a result of the detection.
The structure of the switching circuit 30 having the structure composed of the intelligent power switch will now be described. The switching circuit 30 has a structure similar to that of the switching circuit 11 shown in FIG. 10 except that the switching circuit 30 has the abnormal-signal output portion 41. The switching circuit 30 supplies the power supply voltage VB to the .pi.MOS-FET 32 through the power supply terminal 12 connected to the fusible link 9 (see FIG. 9) and turns on/off the .pi.MOS-FET 32 by a driver 33 thereof.
The switching circuit 30 is provided with an excess voltage detection circuit 34 for detecting a fact that the power supply voltage VB has an excessive voltage level, an electric current detection circuit 35 for detecting an excess current by subjecting the voltage level obtained in accordance with the level of an electric current which flows between the drain and the source of the .pi.MOS-FET 32 and reference voltage Vref supplied from the reference-voltage generating circuit 33A to a comparison so as to detect an excess current, and a temperature detection circuit 36 for detecting overheat of the .pi.MOS-FET 32 by subjecting temperature voltage level V.sub.T obtained from a temperature sensor (not shown) disposed adjacent to the .pi.MOS-FET 32 and the reference voltage Vref to a comparison. Results of detection performed by the detection circuits 34, 35 and 36 are supplied to a negative OR circuit 37. The negative OR circuit 37 is supplied with the control voltage V.sub.IN through an inverter 38.
An output from the negative OR circuit 37 is supplied to the driver 33 and a charge pump 39. The charge pump 39 is operated only when the output from the negative OR circuit 37 is positive logic so as to raise the level of power supply voltage V.sub.DD stabilized by a regulator 40 so as to supply the power supply voltage V.sub.DD to the driver 33. In a case where the output from the negative OR circuit 37 is positive logic, the driver 33 supplies, to the gate of the .pi.MOS-FET 32, control voltage, the level of which turns the .pi.MOS-FET 32 on, and in a case where the output from the negative OR circuit 37 is negative logic, the driver 33 supplies, to the gate of the .pi.MOS-FET 32, control voltage, the level of which turns the .pi.MOS-FET 32 off.
Thus, in the switching circuit 30, similarly to the foregoing switching circuit 11, in a case where excessively high voltage is applied to the .pi.MOS-FET 32, an excess current flows in the .pi.MOS-FET 32 or the .pi.MOS-FET 22 is overheated in a state where the control voltage V.sub.IN is positive logic, the switching operation of the .pi.MOS-FET 32 can be controlled to be switched off. As a result, damage of the .pi.MOS-FET 32 can be prevented.
The switching circuit 30 supplies output voltage V.sub.OUT to the abnormal-signal output portion 41 through an inverter 44. The abnormal-signal output portion 41 has an n-channel MOS-FET 41A. The MOS-FET 41A is turned off when the .pi.MOS-FET 32 has been turned on and thus the level of the output voltage VOUT has been raised. On the other hand, the MOS-FET 41A is turned on when the .pi.MOS-FET 32 has been turned off and thus the level of the output voltage V.sub.OUT has been lowered. A drain terminal 41B of the MOS-FET 41A is pulled up.
Therefore, the CPU 42 (see FIG. 8) is able to determine that the protective function is not operated (that is, no abnormality) in the switching circuit 30 when no potential difference takes place between the drain terminal 41B of the MOS-FET 41A and the source terminal 41C of the same. If a potential difference takes place between the drain terminal 41B and the source terminal 41C, the CPU 42 is able to determine that the protective function is operated (that is, abnormality takes place) in the switching circuit 30.
In each of the foregoing conventional switching circuits 11 and 30 having the protective function, even if a rush current flows when electric power has been supplied to the load, the excess current protective function for protecting the semiconductor switches 15 and 32 is operated. Therefore, there arises a problem in that electric power cannot be supplied to the load when the electric power is supplied.
The foregoing problem will now be described with reference to FIG. 12. FIG. 12 shows change in the electric current level in a semiconductor switch having a rated electric current level of about 10 A!. In a case where a semiconductor switch of the foregoing type is employed, excess current detection threshold Th is, in general, set to about 20 A! (that is, the reference voltage Vref of each of the comparator 20 and the electric current detection circuit 35 is set to a value corresponding to the electric current value of 20 A!). If an electric current, the level of which is higher than the excess current detection threshold Th, flows, the semiconductor switch is switched off.
As a result, the semiconductor switch can be protected from an excess current generated owing to falling of a load, rare short or the like. However, as can be understood from the drawing, at times the rush current will be higher than the excess current detection threshold Th. Therefore, the semiconductor switch is unintentionally switched off when rush current flows.
The semiconductor switch having the rated current level of about 10 A! has a risk that the semiconductor switch is damaged if an electric current of about 20 A! or higher flows continuously attributable to falling of a load or rare short. In general, no damage will occur if the flow takes place in a very short time or if an electric current lower than 80 A! flows. The rush current generally flows for only a short period of time of about one second. Moreover, the level usually is not higher than 80 A!. Therefore, it is unlikely that the semiconductor switch will be damaged by the rush current. As a result, it can be considered that the structure in which the semiconductor switch is switched off by the rush current is not necessary in view of protecting the semiconductor switch.